The invention relates to the field of neural recording amplifier, and in particular to an ultra-low-power neural recording amplifier.
Large-scale chronic multi-electrode neural-recording systems are being built to enable us to understand how the brain works. With the help of such systems, a number of experiments have shown that it is possible to predict intended limb movements by simultaneously recording from many neurons, and interpreting their cortical activities. For example, brain-machine interfaces are being built to help a paralyzed patient move a computer cursor by thoughts alone. Portable, chronic use of such interfaces may eventually play an important role in treatment of paralyzed patients, and enable large-scale monitoring of the brain in experimental neuroscience.
One of the most important parts in the development of brain-machine interfaces is the neural signal amplifier. Neural signals from extracellular recording are very weak (typically between 10 μV and 500 μV). As a result, amplification is needed before such signals can be processed further. Next generation multi-electrode recording systems will be entirely implanted within the skull and incorporate a large number of neural amplifiers (on the order of 100-1000, one for every electrode). For such applications, ultra-low-power operation is very important to minimize heat dissipation in the brain, preserve long-battery life, and maximize the time between recharges. To get clean neural signal recordings, it is important that the input-referred noise of the amplifier be kept low. Practically, the input-referred noise of the amplifier should be kept below the background noise of the recording site (5 μV-10 μV). However, designers must address the tradeoff between low-noise and low-power designs of the amplifier. For an ideal thermal noise-limited amplifier with a constant bandwidth and supply voltage, the power of the amplifier scales as 1/υ2n where υn is the input-referred noise of the amplifier. This relationship shows the steep power cost of achieving low-noise performance in an amplifier.
Many designs of neural amplifiers have been reported in the literature. Most amplifiers consume power near 100 μW to achieve less than 10 μV Vrms input-referred noise for bandwidths of 5-10 kHz. The designs consume power near 100 μW to achieve about 8-9 μVrms input-referred noise with approximately 10 kHz of bandwidth. The design in [8] achieves an input-referred noise of 2.2 μV Vrms with 7.2 kHz of bandwidth while consuming 80 μW of power. If such amplifiers are to be used in a multi-electrode array, with a power near 100 μW per amplifier for most designs, the power required for the neural amplifiers can become the limiting factor for the whole multi-electrode system.
The best prior design presents many useful techniques for designing a neural amplifier: The use of an MOS-bipolar pseudoresistor element as a high-resistance element and on-chip AC-coupling capacitors enable the amplifier to reject large DC offsets at electrode-tissue interfaces while being able to pass the neural signals of interest. Since high-resistance elements can be implemented in a small area on chip, large off-chip components are not needed. The amplifier in uses a standard wide-output swing operational transconductance amplifier (OTA) with capacitive feedback to realize a gain of approximately 40 dB, and presents design techniques that minimize the input-referred noise of the amplifier by operating some devices of the OTA in strong inversion to minimize their noise contributions. Even though the latter design achieves a power-noise tradeoff near theoretical limit of its particular OTA topology, the topology used is not power-efficient since a large portion of the current in it is wasted in its current mirrors. The power efficiency of an amplifier can be greatly improved if a new OTA topology that makes efficient use of the supply current can be created.